Remove ImplicitInvalidate - now users must explicitly assign DontCare to a module, at instantiation site, rather than this happening automatically because the module extended ImplicitInvalidate. Remove ImplicitInvalidate (by in #3096).Remove two unused SFC annotations (by in #3102).Users should instead now extend Module or BlackBox. Remove LegacyModule and LegacyBlackBox (by in #3058).Removed CompileOptions trait and associated code, as it is now unnecessary. Remove compile options everywhere in Chisel internals.Removal of Chisel and the NotStrict compile options. Removed innards and NotStrict for CompileOptions, and object Chisel (by in #3055).Remove SFC Compiler from FIRRTL Subtree (by in #2984).Build FIRRTL in-tree, not published dependency (by in #2983).Add Top-level parameterized reset type (backport #3276) (by in #3282)Īdd a HasParameterizedResetType to mix into Modules for their top level.Ensure that errors in DataView show the problematic fields in a deterministic order.viewAsSupertype to work on Records, with additional tests. viewAsSupertype to work on Records (backport #3267) (by in #3269) Allow DataView of Reset (backport #3181) (by in #3259).out of scope, unwritable sinks) to throw at end of elaboration Connectable's now register erroneous connections (e.g.as, a useful function on Connectable when users to upcast the Scala type. squeezeAllAs, a useful function on Connectable when users want a connection to always squeeze, as well as upcast if desired. unsafe, a useful function on Connectable when users want a connection to "try its best but don't error". Added more Connectable customization functions (backport #3227) (by in #3231).
SyncReadMem.readWrite(address, writeData, enabled, isWrite) explicitly generates a read-write port that supports both read and write access to the memory. Implement read-write memory accessors for SyncReadMem (backport #3190) (by in #3214).
#Scala version Patch
Patch VecInit.fill(0) invocation to successfully compile and yield a zero-width Vec (by in #3171)įix VecInit.fill(0) calls so that they compile and yield 0-width Vecs.Add an annotation for specifying module port conventions (by in #3030).exclude mechanism on Connectable to enable never connecting to/from the marked fields using any connectable operator. exclude to Connectable (by in #3172)Īdded. More Circt intrinsic wrappers (IsX, PlusArgsTest, PlusArgsValue) (by in #2958).This gives a flexible way to generate a stable name for a Chisel type, which is useful for problems like generating stable names for Modules and Queues Implement typeName API for stable Module names (by in #3130).Generate implementation-specific intirnsics.
#Scala version license
#Scala version simulator
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